1. Field of the Invention
This disclosure relates to circuit substrates and packages including such circuit substrates. More particularly, the disclosure relates to circuit substrates having improved warpage preventing properties and methods of manufacturing warpage preventing circuit substrates and packages having the warpage preventing circuit substrates.
2. Description of the Related Art
Modern electronic devices require small size, large memory capacity and high performance for their applications such as mobile applications. Consequently, semiconductor chip packages that go into modern electronic devices, such as mobile electronic devices, also have to have small size, large memory capacity, and high performance. Typically, semiconductor chip packages are either a lead frame type or a Ball Grid Array (BGA)/Land Grid Array (LGA) type. A printed circuit board (PCB) or film substrate is often used in conjunction with a BGA/LGA type package to obtain high reliability and reduced size and weight of the semiconductor chip package.
A PCB includes an insulating substrate, which is typically made of a polyimide material, and a conductive pattern, which is typically made of copper (Cu). The conductive pattern can be disposed in between layers of the substrate or it may be disposed on one of the substrate surfaces. When a chip package is used in an electronic system, such as the main board in a mobile electronic device, the package may be subjected to a heat step for bonding purposes. As a result of the heat step, package warping may occur due to the coefficient of thermal expansion (CTE) mismatch between the various components in the chip package. These components include the semiconductor chip, the substrate, and the molding compound.
FIG. 1 shows a conventional semiconductor chip package design. A semiconductor chip 20 is disposed on a circuit substrate 10. The chip 20 is coupled to a conductive pattern 22 through a wire 16. One end of the wire is connected to a chip pad 18 and the other end of the wire is connected to a bond finger 14. A dummy pattern 12 is disposed on the substrate 10 to increase the strength of the substrate 10 as disclosed in U.S. Pat. No. 6,864,434. The dummy pattern 12 can be connected to a power or a ground lead of the semiconductor chip package. The conductive pattern 22 may include solder ball pads, upon which solder balls can be formed. The solder balls may be formed by applying a solder paste to the solder ball pads and using a heat step to form the solder balls from the solder paste.
FIG. 2 is a cross-sectional view of a semiconductor chip package mounted on a circuit board 40, showing warpage at the edges of the chip package. A conventional process for manufacturing an electronic device having a semiconductor chip includes attaching a semiconductor chip 20 to a circuit substrate 10. The semiconductor chip is then connected electrically to the circuit substrate 10 by a wire 16. This step may be accomplished by a standard wire-bonding process, as is known in the art. Next, the semiconductor chip 20 and the wire 16 are encapsulated by an epoxy molding compound (EMC) 50. Solder balls or solder bumps 30 are then attached to the circuit substrate 10. Next, a singulation step is performed to separate individual semiconductor chip packages from each other. This step may be accomplished by a wafer dicing process. Finally, the solder balls or solder bumps 30 are used to attach the chip package to a circuit board 40. This step may include a heat treatment to melt the solder balls or to melt other conductive material, such as solder paste, for attaching the chip package to the circuit board.
One problem with the conventional semiconductor chip package design is that heat steps used to either form solder balls or join the chip package to the circuit board can cause warpage of the chip package, as shown at “a” in FIG. 2. This warpage can be due to the CTE mismatch between the semiconductor chip 20, the circuit substrate 10, and the EMC 50. This warpage can lead to open connection failures between the chip package and the circuit board as illustrated in a center area of the circuit board of FIG. 2. Further, the stress resulting from the difference in CTE of the materials in the thickness direction of the substrate (i.e. the substrate material, the conductive pattern, and the dummy pattern) can also play a major role in causing warpage of the chip package.
FIGS. 3a and b are stress contour graphs of the circuit substrate 10 during a heat treatment process to mount the chip package to the circuit board. The darker areas of FIGS. 3a and b indicate areas of higher stress. As shown in the figures, the corners and the center areas of the circuit substrate have relatively higher stress concentration than the other areas of the circuit substrate 10. However, as the semiconductor chip 20 is in the center area of the circuit substrate 10 and can therefore resist the stress concentration in the center area, the stress in the center area of the circuit substrate 10 is relatively small. There is, however, not enough resistance to offset the stress at the corners of the circuit substrate 10. Therefore, the stress at the corners of the circuit substrate 10 leads to warpage. Further, the conductive pattern and the dummy pattern, being made of copper, have a high CTE, or high shrinkage rate, thereby causing additional concentration of stress at the corners.
In other words, stress is concentrated at the four corners of the circuit substrate 10 as indicated at “b”. As the thermal expansion or shrinkage rate of the chip 20 is relatively low, the chip 20 opposes the stress generated between the circuit substrate 10 and EMC 50. Therefore, warpage of the area of the circuit substrate 10 where the chip 20 is attached is relatively small. In contrast, in the region “b”, there is not enough stress resistant material such as the chip 20 to oppose the stress. Thus, the stress is applied without much resistance. In particular, the conductive patterns, which have a higher shrinkage rate, cause thermal stress directed toward the corners of the circuit substrate 10. Moreover, the dummy pattern 12 increases the shrinkage of the circuit substrate 10 even higher, thereby increasing the warpage in the region “b”. Such warpage causes non-uniform height of the solder balls 30 against the board 40 during mounting, thereby causing contact failures as illustrated in FIG. 2 as discussed above.
One method to prevent warpage of a chip package is disclosed in JP 2000-151035 ('035). '035 teaches a warpage preventive pattern disposed on a PCB. Another approach to prevent warpage is disclosed in U.S. Pat. No. 6,864,434, as mentioned above.
These conventional methods do not account for the different directions of stress lines that may be concentrated at the different corners of the substrate. Consequently, the stress may not be as effectively reduced at the corners of the substrate. The invention addresses these and other disadvantages of the conventional art.